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CA3290, CA3290A
Data Sheet September 1998 File Number 1049.3
BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output
The CA3290A and CA3290 types consist of a dual voltage comparator on a single monolithic chip. The common mode input voltage range includes ground even when operated from a single supply. The low supply current drain makes these comparators suitable for battery operation; their extremely low input currents allow their use in applications that employ sensors with extremely high source impedances. Package options are shown in the table below.
Features
* MOSFET Input Stage - Very High Input Impedance (ZIN) . . . . . . . . 1.7T (Typ) - Very Low Input Current at V+ = 5V . . . . . . . 3.5pA (Typ) - Wide Common Mode Input Voltage Range (VICR) Can Be Swung 1.5V (Typ) Below Negative Supply Voltage Rail - Virtually Eliminates Errors Due to Flow of Input Currents * Output Voltage Compatible with TTL, DTL, ECL, MOS, and CMOS Logic Systems in Most Applications
Applications
* * * * * High Source Impedance Voltage Comparators Long Time Delay Circuits Square Wave Generators A/D Converters Window Comparators
Pinout
CA3290/A (PDIP) TOP VIEW
OUTPUT (A1) 1 INV. INPUT (A1) 2 NON-INV. INPUT (A1) 3 V- 4
A1
8 V+
+A2
7 OUTPUT (A2)
Schematic Diagram
(ONLY ONE IS SHOWN)
BIASING CIRCUIT FOR CURRENT SOURCES COMPARATOR NO. 1 V+
D1 D2 Q1 +VI -VI Q2 Q3
1
-+
6 INV. INPUT (A2) 5 NON-INV. INPUT (A2)
Ordering Information
PART NUMBER CA3290AE CA3290E TEMP RANGE (oC) -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld PDIP PKG. NO. E8.3 E8.3
TO COMP. NO. 2
I1 Q9 50A
I2 Q10
I3
I4 Q11 100A Q12 VO D3 D4 Q4 Q8 Q15 Q17 R1 100k Q7 R2 1k Q18 Q16 Q13 Q14
100A
50A
Q5
Q6 R3 5k C1 5pF
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
CA3290, CA3290A
Absolute Maximum Ratings
Supply Voltage Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36V Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Differential Input Voltage . . . . . . . . . . . . . . . . 36V or [(V+ - V-) +5V] (whichever is less) DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V+ +5V to V- -5V Output to V- Short Circuit Duration (Note 1) . . . . . . . . . .Continuous Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Short circuits from the output to V+ can cause excessive heating and eventual destruction of the device. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Input Offset Voltage
V- = 0V, Unless Otherwise Specified TEMP (oC) Full Full 25 25 CA3290A MIN VCM = 1.4V, V+ = 5V VCM = 0V, V+ = +15V, V- = -15V VCM = 1.4V, V+ = 5V VCM = 0V, V+ = +15V, V- = -15V Full Full 25 25 125 125 25 25 -55 -55 25 25 Full 25 25 88 TYP 4.5 8.5 4.0 4.0 8 2 7 2 7 2.8 13 3.5 12 0.85 1.62 0.8 1.35 150 103 800 118 MAX 10 10 28 28 25 25 45 45 40 40 1.0 3.0 1.4 3.0 MIN 25 88 CA3290 TYP 8.5 8.5 7.5 7.5 8 2 7 2 7 2.8 13 3.5 12 0.85 1.62 0.8 1.35 150 103 800 118 MAX 20 20 32 32 30 30 55 55 50 50 1.6 3.5 1.4 3.0 UNITS mV mV mV mV V/oC nA nA pA pA nA nA pA pA mA mA mA mA V/mV dB V/mV dB
SYMBOL VIO
TEST CONDITIONS VCM = VO = 1.4V, V+ = 5V VCM = VO = 0V, V+ = +15V, V- = -15V VCM = VO = 1.4V, V+ = 5V VCM = VO = 0V, V+ = +15V, V- = -15V
Temperature Coefficient of Input Offset Voltage Input Offset Current
VIO/T IIO
Input Current
II
VCM = 1.4V, V+ = 5V VCM = 0V, V+ = +15V, V- = -15V VCM = 1.4V, V+ = 5V VCM = 0V, V+ = +15V, V- = -15V
Supply Current
I+
RL = , V+ = 5V RL = , V+ = 30V RL = , V+ = 5V RL = , V+ = 30V
Voltage Gain
AOL
RL = 15k, V+ = +15V, V- = -15V RL = 15k, V+ = +15V, V- = -15V
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CA3290, CA3290A
Electrical Specifications
PARAMETER Saturation Voltage V- = 0V, Unless Otherwise Specified (Continued) TEMP (oC) 125 -55 25 Full Full 25 25 25 25 25 25 25 25 25 25 25 25 CA3290A MIN V+ -3.5 VV+ -3.8 V6 TYP 0.22 0.1 0.12 65 130 100 500 V+ -3.1 V- -1.5 V+ -3.4 V- -1.6 44 100 15 30 1.2 200 500 400 MAX 0.7 0.4 1k 562 562 316 MIN V+ -3.5 VV+ -3.8 V6 CA3290 TYP 0.22 0.1 0.12 65 130 100 500 V+ -3.1 V- -1.5 V+ -3.4 V- -1.6 44 100 15 30 1.2 200 500 400 MAX 0.7 0.4 1k 562 562 316 UNITS V V V nA nA pA pA V V V/V V/V V/V mA s ns ns ns
SYMBOL VSAT
TEST CONDITIONS ISINK = 4mA, V+ = 5V, +VI = 0V, -VI = 1V ISINK = 4mA, V+ = 5V, +VI = 0V, -VI = 1V ISINK = 4mA, V+ = 5V, +VI = 0V, -VI = 1V
Output Leakage Current
IOL
V+ = 15V V+ = 36V V+ = 15V V+ = 36V
Common Mode Input Voltage Range
VICR
VO = 1.4V, V+ = 5V VO = 0V, V+ = +15V, V- = -15V
Common Mode Rejection Ratio Power Supply Rejection Ratio Output Sink Current Response Time Rising Edge Response Time Falling Edge Large Signal Response Time
CMRR
V+ = +15V, V- = -15V V+ = 5V
PSRR
V+ = +15V, V- = -15V VO = 1.4V, V+ = 5V
tr tf
RL = 5.1k, V+ = 15V RL = 5.1k, V+ = 15V RL = 5.1k, V+ = 15V RL = 5.1k, V+ = 5V
Test Circuits and Waveforms
CC = 2pF +15V +15V 1K + VIN TO 10X SCOPE PROBE
1K -15V
WITH CC Top Trace 4.5mV/Div. = VIN Bottom Trace = 10V/Div. = VOUT Time Scale = 5s/Div.
WITHOUT CC Top Trace 4.5mV/Div. Bottom Trace = 10V/Div. Time Scale = 5s/Div.
FIGURE 1. PARASITIC OSCILLATIONS TEST CIRCUIT AND WAVEFORMS
3
CA3290, CA3290A Test Circuits and Waveforms
INPUT OVERDRIVE +15V GND
INPUT OVERDRIVE GND
1K INPUT 1K +
5.1K
-
OUTPUT
100mV OVERDRIVE
20mV OVERDRIVE
5mV OVERDRIVE
5mV OVERDRIVE
20mV OVERDRIVE
100mV OVERDRIVE
FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
GND +15V INPUT OVERDRIVE 5.1K + OUTPUT 1K 5mV OVERDRIVE 20mV OVERDRIVE 100mV OVERDRIVE
GND INPUT OVERDRIVE
1K INPUT
-
100mV OVERDRIVE
20mV OVERDRIVE
5mV OVERDRIVE
FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
Circuit Description
The Basic Comparator
Figure 4 shows the basic circuit diagram for one of the two comparators in the CA3290. It is generically similar to the industry type "139" comparators, with PMOS transistors replacing PNP transistors as input stage elements. Transistors Q1 through Q4 comprise the differential input stage, with Q5 and Q6 serving as a mirror connected active load and differential-to-single-ended converter. The differential input at Q1 and Q4 is amplified so as to toggle Q6 in accordance with the input signal polarity. For example, if +VIN is greater than -VIN, Q1, Q2, and current mirror transistors Q5 and Q6 will be turned off; Transistors Q3, Q4, and Q7 will be turned on, causing Q8 to be turned off. The output is pulled positive when a load resistor is connected between the output and V+. In essence, Q1 and Q4 function as source followers to drive Q2 and Q3, respectively, with zener diodes D1 through D4 providing gate oxide protection against input voltage transients (e.g., static electricity). The current flow in Q1 and Q4 is established at approximately 50A by constant current sources I1 and I3, respectively. Since Q1 and Q4 are operated with a constant current load, their gate-to-source voltage drops will be effectively constant as long as the input voltages are within the common-mode range. As a result, the input offset voltage (VGS(Q1) + VBE(Q2) VBE(Q3) - VGS(Q4)) will not be degraded when a large differential DC voltage is applied to the device for extended periods of time at high temperatures. Additional voltage gain following the first stage is provided by transistors Q7 and Q8. The collector of Q8 is open, offering the user a wide variety of options in applications. An additional discrete transistor can be added if it becomes necessary to boost the output sink current capability. The detailed schematic diagram for one comparator and the common current source biasing is shown on the front page. PMOS transistors Q9 through Q12 are the current source elements identified in Figure 4 as I1 through I4, respectively.
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CA3290, CA3290A
Their gate source potentials (VGS) are supplied by a common bus from the biasing circuit shown in the right hand portion of the Schematic Diagram. The currents supplied by Q10 and Q12 are twice those supplied by Q9 and Q11. The transistor geometries are appropriately scaled to provide the requisite currents with common VGS applied to Q9 through Q12.
V+ I1 50A D1 D2 I2 100A I3 50A D3 D4 Q8 QP4 Q5 Q6 VIQ7 I4 100A VO
minimize the stray capacitive coupling between the input and output terminals. Parasitic oscillations manifest themselves during the output voltage transition intervals as the comparator switches states. For high source impedances, stray capacitance can induce parasitic oscillations. The addition of a small amount (1mV to 10mV) of positive feedback (hysteresis) produces a faster transition, thereby reducing the likelihood of parasitic oscillations. Furthermore, if the input signal is a pulse waveform, with relatively rapid rise and fall times, parasitic tendencies are reduced. When dual comparators, like the CA3290, are packaged in an 8 lead configuration, the output terminal of each comparator is adjacent to an input terminal. The lead-to-lead capacitance is approximately 1pF, which may be sufficient to cause undesirable feedback effects in certain applications. Circuit factors such as impedance levels, supply voltage, switching rate, etc., may increase the possibility of parasitic oscillations. To minimize this potential oscillatory condition, it is recommended that for source impedances greater than 1k a capacitor (1pF - 2pF) be connected between the appropriate input terminal and the output terminal. (See Figure 1.) If either comparator is unused, its input terminals should also be tied to either the V+ or V- supply rail.
VI+
QP1
Q2
Q3
V-
FIGURE 4. BASIC CIRCUIT DIAGRAM FOR ONE OF THE TWO COMPARATORS
Operating Considerations
Input Circuit
The use of MOS transistors in the input stage of the CA3290 series circuits provides the user with the following features for comparator applications: 1. Ultra high input impedance (1.7T); 2. The availability of common mode rejection for input signals at potentials below that of the negative power supply rail; 3. Retention of the in phase relationship of the input and output signals for input signals below the negative rail. Although the CA3290 employs rugged bipolar (zener) diodes for protection of the input circuit, the input terminal currents should not exceed 1mA. Appropriate series connected limiting resistors should be used in circuits where greater current flows might exist, allowing the signal input voltage to be greater than the supply voltage without damaging the circuit.
Typical Applications
Light Controlled One-Shot Timer
In Figure 5 one comparator (A1) of the CA3290 is used to sense a change in photo diode current. The other comparator (A2) is configured as a one-shot timer and is triggered by the output of A1. The output of the circuit will switch to a low state for approximately 60 seconds after the light source to the photo diode has been interrupted. The circuit operates at normal room lighting levels. The sensitivity of the circuit may be adjusted by changing the values of R1 and R2. The ratio of R1 to R2 should be constant to insure constant reverse voltage bias on the photo diode.
R1 1.5M +15V +15V +15V
Output Circuit
The output of the CA3290 is the open collector of an n-p-n transistor, a feature providing flexibility in a broad range of comparator applications. An output ORing function can be implemented by parallel connection of the open collectors. An output pull-up resistor can be connected to a power supply having a voltage range within the rating of the particular CA3290 in use; the magnitude of this voltage may be set at a value which is independent of that applied to the V+ terminal of the CA3290.
15k 1M 15 k 3 2 C30809 +15V 8 + A1 CA3290 1 140k +15V 6 4 0.01F 1N914 60M 5 1.0F 1N914 3.3k
R2 2M
+ A2 CA3290 7
-
10k X 60s TIME
Parasitic Oscillations
The ideal comparator has, among other features, ultra high input impedance, high gain, and wide bandwidth. These desirable characteristics may, however, produce parasitic oscillations unless certain precautions are observed to
FIGURE 5. LIGHT CONTROLLED ONE-SHOT TIMER
5
CA3290, CA3290A
Low-Frequency Multivibrator
In this application, one half of the CA3290 is used as a conventional multivibrator circuit. Because of the extremely high input impedance of this device, large values of timing resistor (R1) may be used for long time delays with relatively small leakage timing capacitors. The second half of the CA3290 is used as an output buffer to insure that the multivibrator frequency will not be affected by output loading. RP is the parallel combination of the two 1M resistors connected between +15V and GND.
+15V +15V R1 20M 1M C 2 0.36 F RP 1M 3 8 +15V +15V 15k + 3.3k INPUT 5 A1 1 1M 1M 4 4 6 A2 7 100k 5 R2 47k +15V R1 VU 47k 3 R3 6.8k 6 VL A2
Window Comparator
Both halves of the CA3290 can be used in a high input impedance window comparator as shown in Figure 7. The LED will be turned "on" whenever the input signal is above the lower limit (VL) but below the upper limit (VU), as determined by the R1/R2/R3 resistor divider.
+15V
8 100k 2
A1 CA3290 +
3.9k 1
LED
670
2N2102
CA3290
CA3290 + 7
+
-
CA3290
t = Period = 10s 2R P t = 2R 1 Clog e ----------- + 1 R2 FIGURE 7. WINDOW COMPARATOR
R2 1M
FIGURE 6. LOW FREQUENCY MULTIVIBRATOR
Typical Performance Curves
4.0 3.5 SUPPLY CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 TOTAL SUPPLY VOLTAGE (V) -55oC 25oC 125oC INPUT CURRENT (pA) RL = 0 -5 -10 -15 -20 -25 -30 TA = 25oC V+ = +30V, V- = GND
0
5
10
15
20
25
30
35
INPUT COMMON MODE VOLTAGE (V)
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE (BOTH AMPLIFIERS)
FIGURE 9. INPUT CURRENT vs INPUT COMMON MODE VOLTAGE
6
CA3290, CA3290A Typical Performance Curves
TA = 25oC V+ = +5V, V- = GND 4.5 INPUT CURRENT (pA) 4.0 3.5 3.0 2.5
(Continued)
INPUT EXCURSIONS FROM V+ TERMINAL (V)
-1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 125oC 25oC -55oC
0
1.0
2.0
3.0
4.0
5.0
0
5
10
15
20
25
30
35
40
45
INPUT COMMON MODE VOLTAGE (V)
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 10. INPUT CURRENT vs INPUT COMMON MODE VOLTAGE
FIGURE 11. POSITIVE COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
INPUT EXCURSIONS FROM V- TERMINAL (V)
10K 1.0 INPUT CURRENT (pA) 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 0 25oC -55oC 1 5 10 15 20 25 30 35 40 45 0 20 40 60 80 100 120 140 NEGATIVE SUPPLY VOLTAGE (V) TEMPERATURE (oC) 125oC 1K V+ = 5V, V- = 0V VCM = 1.4V V+ = +15V, V- = -15V VCM = 0V
100
10
FIGURE 12. NEGATIVE COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
10V OUTPUT SATURATION VOLTAGE
FIGURE 13. INPUT CURRENT vs TEMPERATURE
125oC 25oC -55oC
1V
100mV
125oC 25oC -55oC
10mV
1mV 10A
100A 1mA 10mA OUTPUT SINK CURRENT
FIGURE 14. OUTPUT SATURATION VOLTAGE vs OUTPUT SINK CURRENT
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CA3290, CA3290A Metallization Mask Layout
0 90 80 7 70 60 10 50 40 11 12 30 20 10 1 0 4 6 10 20 30 40 50 53
87 - 95 (2.210 - 2.403)
The photographs and dimensions of each chip represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.17mm) larger in both dimensions. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) NOTE: Numbers in pads are for 8 lead DIP and TO-5 Can and numbers outside of chip are for 14 lead DIP.
4 - 10 (0.102 - 0.254) 50 - 58 (1.270 - 1.473)
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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